
This Senior Member of Technical Staff role focuses on IO and clocking design engineering within Micron's IP Design team, contributing to high-speed circuits for DRAM memory products. The position involves defining and optimizing high-speed interfaces, analyzing timing and jitter sensitivity, and developing simulation methodologies to ensure performance at full-chip and system levels. Key responsibilities include collaborating with product and signal integrity teams to correlate silicon results and working with process integration groups on next-generation nodes. The role appeals to engineers seeking to drive innovation in semiconductor technology while mentoring junior staff. It offers a collaborative environment dedicated to professional growth and employee wellbeing. Relocation to the Boise, Idaho headquarters is required for this on-site position.














