SMTS, IO/Clock Design Engineering
Not Disclosed•Full-TimeOn-site
location_on690, South 13th Street, Downtown, Boise, Ada County, Idaho, 83702, United States
About Micron Technology
Our vision is to transform how the world uses information to enrich life for all. As a world leader in innovating memory and storage solutions, we accelerate the transformation of information into intelligence, inspiring the world to learn, communicate, and advance faster than ever.
About the Role
We are seeking an experienced IO/Clocking Design Engineer at the SMTS level to join our IP Design team. In this role, you will contribute to the development of critical high-speed IP circuits used across Micron's DRAM memory products. You will focus on equalization and bandwidth extension to push the limits of circuit and process performance, analyzing IO impairments, clock jitter, and duty cycle distortion to assess their impact on DRAM system timing. This position requires developing core strategies and implementing effective engineering solutions to address complex challenges in high-speed design.
Relocation to Micron's headquarters in Boise, Idaho, is required for this position.
Our Culture and Benefits
As a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and professional growth. We offer a choice of medical, dental, and vision plans in all locations, allowing team members to select the plans that best meet their family healthcare needs and budget. Our benefit programs also include income protection if you are unable to work due to illness or injury, paid family leave, a robust paid time-off program, and paid holidays.
Equal Opportunity and Application
Micron is proud to be an equal opportunity workplace and an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity, or any other factor protected by applicable federal, state, or local laws.
For US sites only, to request assistance with the application process or for reasonable accommodations, please contact Micron's People Organization at hrsupport_na@micron.com or 1-800-336-8918 (select option #3).
Important Application Notes:
- AI Usage: Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.
- Fraud Alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website.
- Labor Standards: Micron prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards. Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment.
To learn more about Micron, please visit micron.com/careers.
Work location
Work model: On-site
690, South 13th Street, Downtown, Boise, Ada County, Idaho, 83702, United States
Boise, Idaho
Key Responsibilities
- check_circleDefine, innovate, design, optimize and verify high-speed IO and clocking circuits for new DRAM products
- check_circleApply robust high-speed circuit design techniques to enhance timing and jitter sensitivity analysis
- check_circleSupervise layout work and ensure good layout practices to minimize parasitic impacts
- check_circleMentor and coach engineers early in their careers
- check_circleCollaborate with Product Engineering and SI teams to correlate silicon performance with simulation results
- check_circleDevelop accurate modeling, analysis and simulation methodologies for circuit performance metrics
- check_circleWork with process integration and transistor modeling teams on next-generation process nodes
Requirements
- verifiedMinimum MSEE + 10 years industry experience or BSEE + 12 years industry experience
- verifiedStrong background in designing high-speed IO interface, timing and clocking circuits
- verifiedProven silicon successes
- verifiedAbility to supervise layout work and understand good layout practices for high-speed circuits
- verifiedDemonstrated ability in mentoring and coaching engineers
- verifiedPrior experience in DRAM circuit design
- verifiedPrior experience in channel modeling and characterization, transceiver noise and timing budget analysis, equalization techniques, SI knowledge
- verifiedUnderstanding of device physics and basic CMOS processing techniques
- verifiedDemonstrated ability with AI/ML usage
- verifiedFluency in scripting languages such as PERL/Python
Nice to Have
Prior experience in DRAM circuit design. Prior experience in channel modeling and characterization, transceiver noise and timing budget analysis, equalization techniques, and SI knowledge. Understanding of device physics and basic CMOS processing techniques. Demonstrated ability with AI/ML usage and fluency in scripting languages such as PERL/Python.
Benefits & Perks
check_circleChoice of medical, dental, and vision plans in all locationscheck_circleIncome protection benefits for illness or injurycheck_circlePaid family leavecheck_circleRobust paid time-off program and paid holidays
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Frequently asked questions about SMTS, IO/Clock Design Engineering at Micron Technology
What does a SMTS, IO/Clock Design Engineering at Micron Technology do?expand_more
A SMTS, IO/Clock Design Engineering at Micron Technology is responsible for the following: Define, innovate, design, optimize and verify high-speed IO and clocking circuits for new DRAM products; Apply robust high-speed circuit design techniques to enhance timing and jitter sensitivity analysis; Supervise layout work and ensure good layout practices to minimize parasitic impacts; and Mentor and coach engineers early in their careers.
What are the requirements for this SMTS, IO/Clock Design Engineering role?expand_more
Micron Technology is looking for candidates who meet the following requirements: Minimum MSEE + 10 years industry experience or BSEE + 12 years industry experience; Strong background in designing high-speed IO interface, timing and clocking circuits; Proven silicon successes; Ability to supervise layout work and understand good layout practices for high-speed circuits; Demonstrated ability in mentoring and coaching engineers; and Prior experience in DRAM circuit design.
Where is the SMTS, IO/Clock Design Engineering role at Micron Technology located?expand_more
SMTS, IO/Clock Design Engineering at Micron Technology is based in 690, South 13th Street, Downtown, Boise, Ada County, Idaho, 83702, United States. This is a on-site role.
Is this SMTS, IO/Clock Design Engineering job remote, hybrid, or on-site?expand_more
Micron Technology has listed this SMTS, IO/Clock Design Engineering role as on-site.
How much experience is required for this SMTS, IO/Clock Design Engineering role?expand_more
SMTS, IO/Clock Design Engineering at Micron Technology typically requires 10+ years of relevant experience at the senior level.
What skills do you need for the SMTS, IO/Clock Design Engineering role at Micron Technology?expand_more
Key skills for SMTS, IO/Clock Design Engineering at Micron Technology include High-Speed Io; Clocking Circuits; Timing; Jitter; Duty Cycle Distortion; Equalization; Bandwidth Extension; and Circuit Design.
What category does the SMTS, IO/Clock Design Engineering role belong to?expand_more
SMTS, IO/Clock Design Engineering at Micron Technology is part of the engineering job category on Recrutus.