Global CPU Design Lead, Silicon
Not Disclosed•Full-TimeOn-site
location_onMorrison Bridge, Downtown, Portland, Multnomah County, Oregon, 97204, United States
About the Team
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful, aiming to make people's lives better through technology.
About the Role
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a Global Design Lead, you will join the CPU Silicon Engineering team to architect and deliver the foundational infrastructure that enables our high-performance processors to function. You will own the "global" logic subsystems within the CPU, encompassing clock generation, reset domains, power management integration, and debug/trace fabrics. In this role, you will lead the technical definition and execution of these critical blocks, ensuring they meet rigorous performance requirements and integrate seamlessly into the top-level System-on-Chip (SoC). You will lead a distributed engineering team through the full design life-cycle, from micro-architecture and RTL implementation to logic synthesis and post-silicon bring-up, while collaborating closely with cross-functional partners to resolve integration issues.
Hiring Process
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Equal Opportunity
Google is an equal opportunity employer and values diversity. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.
Work location
Work model: On-site
Morrison Bridge, Downtown, Portland, Multnomah County, Oregon, 97204, United States
Portland, Oregon
Similar Job Opportunities
Skills, education and keywords
Skills: Electrical Engineering, Computer Engineering, Computer Science, Silicon Design, Ip, Cpu, Gpu, Tpu, RTL Design, Soc Infrastructure Design.
Education: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field, or equivalent experience; Master's degree in Electrical Engineering, Computer Engineering, or Computer Science; PhD in Electrical Engineering, Computer Engineering, or Computer Science.
Frequently asked questions about Global CPU Design Lead, Silicon at OPH
What does a Global CPU Design Lead, Silicon at OPH do?expand_more
In this Global CPU Design Lead, Silicon at OPH role, you will lead the micro-architecture, design, and delivery of cpu subsystem infrastructure including clocks, resets, boot, and debug logic; drive the integration of the cpu into the top-level soc while managing standard interfaces and cross-functional dependencies; manage the execution of the design life-cycle from concept to tape-out including logic synthesis and static checks; and collaborate with verification, physical design, and post-silicon validation teams to ensure functionality and successful bring-up.
What are the requirements for this Global CPU Design Lead, Silicon role?expand_more
To qualify for the Global CPU Design Lead, Silicon at OPH position, applicants should have: Bachelors degree in Electrical Engineering, Computer Engineering, Computer Science, or related field; 10 years of experience in silicon design with focus on IP; Experience managing technical teams and RTL design projects to tape-out; Experience with SoC infrastructure design; Masters degree or PhD preferred; and Experience with ARM architecture and AMBA protocols.